1. Field of the Invention
This invention generally relates to electronic devices and methods of fabricating the same, and more particularly, to an electronic device in which device chips are flip-chip mounted and a method of fabricating the same.
2. Description of the Related Art
Wire bonding methods have conventionally been employed for electrically and mechanically coupling chips and a package in electronic devices. In the wire bonding methods, adhesives have been used for mechanically coupling the device chips and the packages, and metal wires have been used for electrical coupling. However, as the devices have been reduced in size and cost, the flip-chip bonding technique with the use of bumps is mainly employed for coupling the chips and the package in these years.
Japanese Patent Application Publication No. 2001-53577 (hereinafter, referred to as Document 1) and Japanese Patent Application Publication No. 2001-110946 (hereinafter, referred to as Document 2) disclose the configurations of the electronic devices fabricated by use of the flip-chip bonding technique described below. Firstly, bumps are formed on the surface of the device chip by use of the metal wires, in advance. The chip with the bumps thereon is mounted on the wiring pattern formed on the surface of a ceramic package substrate by means of a flip-chip bonder. By this, the bumps and the wiring pattern are bonded together. This bonding couples the device chip and the package substrate electrically and mechanically. Then, the electronic device is completed by sealing with a metal lid.
International Publication No. WO 97/02596 (hereinafter, referred to as Document 3) discloses the following technique. The device chip and the package substrate are electrically and mechanically coupled by use of the bumps in a similar manner to Document 1 and Document 2. Subsequently, a sealing resin is provided to cover the device chip, so the device chip is sealed and the outer shape thereof is formed. In this manner, the electronic device is completed.
Japanese Patent Application Publication No. 2004-129193 (hereinafter, referred to as Document 4) discloses the following technique. The device chip and the package substrate are electrically and mechanically bonded by the bumps. At that time, sealing is also performed simultaneously with the sealing solder formed on the surface of the package substrate in advance. Then, the outer shape is formed by use of the sealing resin. In this manner, the electronic device is completed.
The electronic device in which the device chip and the package substrate are bonded as described above may malfunction, if a foreign material comes into contact with the electrode pattern formed on the device chip surface, or if moisture or the like enters from the outside. To prevent the aforementioned malfunction, the cavity hermetic sealing is performed. In particular, since the device chip surface vibrates with elastic waves in a surface acoustic wave filter or the like that utilizes the elastic waves in a surface acoustic wave device or a piezoelectric thin-film resonator, the cavity hermetic sealing is generally employed.
In the techniques described in Document 1 and Document 2, high airtightness and robust outer shape are maintained by using the metal lid and sealing solder. However, side walls have to be formed in the package substrate, making it difficult to reduce the size and cost thereof.
In the technique described in Document 3, the reduction in size and cost is enabled by use of the sealing resin. However, its airtightness is inferior. Also, it is difficult to block off the influence of electric waves from the outside, because the whole device chip is not shielded by metal. This will lead to the degradation in performance as an electronic device for high frequency.
The technique disclosed in Document 4 has a feature of sealing the device by use of the sealing solder and forming the outer shape by use of the sealing resin. This achieves downsizing and high airtightness. However, since the two types of materials and methods are used for sealing and forming the outer shape, it is difficult to reduce the cost. Also, there is a problem in that there are many restrictions on the shape variations, heating period, and the like, because the sealing solder is provided on the package substrate side in advance. If the respective chips are flip mounted on the sheet-shaped multifaceted substrate and the solder sealing is performed simultaneously, the whole sheet has to be heated at 300° C. or more for more than several minutes. It has been found that this heating melted metal layers into the solder, the metal layers being provided in the device chips and the package substrate and being easily blended into solder, thereby degrading the sealing reliability.